This invention relates to frequency synthesizers in general, and more particular, to a fractional-N-frequency synthesizer in which selectable frequency outputs are produced while reducing unwanted spurious outputs. Frequency divider circuits are used in frequency synthesizer circuits such as in a phase lock loop (PLL). In a fractional-N-synthesis PLL circuit, the output frequency f.sub.O of a voltage controlled oscillator (VCO) is first divided and then applied to a phase detector which operates in a conventional manner comparing the phase of the divided output signal with a reference frequency f.sub.r from a reference oscillator, in order to control the VCO output frequency f.sub.O. The output frequency f.sub.O is related to the reference frequency of the reference frequency source by the relationship f.sub.O =(N.F).times.f.sub.r. N.F is the effective divisor by which the output frequency is divided before it is compared with the reference frequency. N.F is produced by a divider control circuit and consists of an integer part N and a fractional part F. The fractional part F=k/D where k and D are both integers.
Since a divider operates with integer values, fractional division is simulated by switching between different integer values of divisors. However, this switching of the divisors results in spurious sidebands in the synthesized output frequency signal f.sub.O. The goal in designing a synthesizer is to keep the amplitudes of these sub-harmonic spurs below some maximum acceptable limit.
An approach, illustrated in U.S. Pat. No. 4,204,174, to cancel unwanted spurious signals utilizes two accumulators to simulate the fractional division and a digital-to-analog converter to generate a correction signal to back-off the resultant spurious sidebands. U.S. Pat. No. 4,694,475 also illustrates the use of two accumulators for a frequency divider circuit. Basically, both methods utilize a first accumulator to correct for phase error and a second accumulator to which the instantaneous contents of the first accumulator is summed at each cycle of the divider output. For each clock cycle in which the second accumulators fixed capacity D is reached, the divisor is increased by one from its programmed value. On each succeeding clock cycle, the divisor N is decreased by one from its programmed value. The net effect on the average divisor is zero since counts are always added and subtracted in pairs. Such two accumulator approaches provide a single unique waveform and associated spurious response for each value of numerator k for the fractional part of the divider and capacity D of the accumulators for a synthesizer of a predetermined loop bandwidth.
The one unique waveform can result in unacceptable spurious signals for a desired output frequency f.sub.O. In some applications, spurious signals with 20 kHz of a desired frequency f.sub.O must be 60 dB below the carrier f.sub.O frequency signal while spurious signals further than 20 kHz from the carrier frequency must be 90 dB below the carrier level. With the waveform provided by prior art two accumulator approaches, the spurious signals can exceed the desired limits. FIG. 6 illustrates such a situation. In this illustration, spur 134 is within desired limits, however, spur 132 exceeds desired limits.
In applications such as two-way radios, minimizing hardware along with eliminating the effects of spurs is of utmost importance.